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| 19-5101; Rev 4; 4/11 Thermochron iButton General Description The DS1921G Thermochron(R) iButton(R) is a rugged, selfsufficient system that measures temperature and records the result in a protected memory section. The recording is done at a user-defined rate, both as a direct storage of temperature values as well as in the form of a histogram. Up to 2048 temperature values taken at equidistant intervals ranging from 1 to 255min can be stored. The histogram provides 63 data bins with a resolution of 2.0C. If the temperature leaves a user-programmable range, the DS1921G also records when this happened, for how long the temperature stayed outside the permitted range, and if the temperature was too high or too low. An additional 512 bytes of read/write nonvolatile (NV) memory allows storing information pertaining to the object to which the DS1921G is associated. Data is transferred serially through the 1-Wire(R) protocol, which requires only a single data lead and a ground return. Every DS1921G is factory lasered with a guaranteed unique, electrically readable, 64-bit registration number that allows for absolute traceability. The durable stainless steel package is highly resistant to environmental hazards such as dirt, moisture, and shock. Accessories permit the DS1921G to be mounted on almost any object including containers, pallets, and bags. Features Digital Thermometer Measures Temperature in 0.5C Increments Accuracy 1C from -30C to +70C (See the Electrical Characteristics for Accuracy Specification) Built-In Real-Time Clock (RTC) and Timer Has Accuracy of 2 Minutes per Month from 0C to +45C Water Resistant or Waterproof if Placed Inside DS9107 iButton Capsule (Exceeds Water Resistant 3 ATM Requirements) Automatically Wakes Up and Measures Temperature at User-Programmable Intervals from 1 Minute to 255 Minutes Logs Up to 2048 Consecutive Temperature Measurements in Protected NV RAM Records a Long-Term Temperature Histogram with 2.0C Resolution Programmable Temperature High and Temperature Low Alarm Trip Points Records Up to 24 Timestamps and Durations When Temperature Leaves the Range Specified by the Trip Points 512 Bytes of General-Purpose Read/Write NV RAM Communicates to Host with a Single Digital Signal at 15.4kbps or 125kbps Using 1-Wire Protocol DS1921G Applications Temperature Logging in Cold Chain, Food Safety, Pharmaceutical, and Medical Products Common iButton Features Digital Identification and Information by Momentary Contact Unique, Factory-Lasered, and Tested 64-Bit Registration Number (8-Bit Family Code + 48-Bit Serial Number + 8-Bit CRC Tester) Assures Absolute Traceability Because No Two Parts are Alike Multidrop Controller for 1-Wire Net Chip-Based Data Carrier Compactly Stores Information Data Can Be Accessed While Affixed to Object Button Shape is Self-Aligning with Cup-Shaped Probes Durable Stainless-Steel Case Engraved with Registration Number Withstands Harsh Environments Easily Affixed with Self-Stick Adhesive Backing, Latched by Its Flange, or Locked with a Ring Pressed Onto Its Rim Presence Detector Acknowledges When Reader First Applies Voltage Meets UL 913, 5th Ed., Rev. 1997-02-24; Intrinsically Safe Apparatus: Approved Under Entity Concept for Use in Class I, Division 1, Group A, B, C, and D Locations 1 Ordering Information PART DS1921G-F5# TEMP RANGE -40C to +85C PIN-PACKAGE F5 iButton #Denotes a RoHS-compliant device that may include lead(Pb) that is exempt under the RoHS requirements. Examples of Accessories PART DS9096P DS9101 DS9093RA DS9093A DS9092 ACCESSORY Self-Stick Adhesive Pad Multipurpose Clip Mounting Lock Ring Snap-In Fob iButton Probe Pin Configuration appears at end of data sheet. Thermochron, iButton, and 1-Wire are registered trademarks of Maxim Integrated Products, Inc. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. Thermochron iButton DS1921G ABSOLUTE MAXIMUM RATINGS IO Voltage Range Relative to GND ..........................-0.5V to +6V IO Sink Current....................................................................20mA *Storage or operation above +50C significantly reduces battery life. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Operating Temperature Range ..........................-40C to +85C* Storage Temperature Range..............................-40C to +50C* ELECTRICAL CHARACTERISTICS (VPUP = +2.8V to +5.25V, TA = -40C to +85C.) PARAMETER IO PIN: GENERAL DATA 1-Wire Pullup Resistance Input Capacitance Input Load Current High-to-Low Switching Threshold (Notes 4, 6, 7, 8) Input Low Voltage Low-to-High Switching Threshold (Notes 4, 6, 7, 10) Output Low Voltage at 4mA RPUP CIO IL VTL VIL VTH VOL (Notes 1, 2) (Notes 3, 4) IO pin at VPUP (Note 5) VPUP > 4.5V (Notes 1, 6, 9) VPUP > 4.5V (Notes 6, 11) Standard speed, RPUP = 2.2k Overdrive speed, RPUP = 2.2k Overdrive speed, directly prior to reset pulse; RPUP = 2.2k Standard speed Overdrive speed Standard speed, VPUP > 4.5V Reset Low Time (Notes 1,12) tRSTL Standard speed Overdrive speed, VPUP > 4.5V Overdrive speed Presence-Detect High Time (Note 12) Presence-Detect Low Time (Note 12) Presence-Detect Sample Time (Notes 1, 4) t PDH Standard speed Overdrive speed Standard speed t PDL Overdrive speed, VPUP > 4.5V Overdrive speed Standard speed Overdrive speed 5 2 5 65 8 480 540 48 58 15 1.1 60 7.5 7.5 60 6 640 640 80 80 60 6 270 24 32 75 8.6 s s s s s s 1.00 0.66 1.14 0.71 100 2.2 800 10 2.70 2.70 0.30 2.70 2.70 0.4 k pF A V V V V SYMBOL CONDITIONS MIN TYP MAX UNITS Recovery Time (Notes 1, 4) tREC Time-Slot Duration (Notes 1, 12) t SLOT IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE tMSP 2 _______________________________________________________________________________________ Thermochron iButton ELECTRICAL CHARACTERISTICS (continued) (VPUP = +2.8V to +5.25V, TA = -40C to +85C.) PARAMETER IO PIN: 1-Wire WRITE Standard speed Write-Zero Low Time (Notes 1, 12, 13) Write-One Low Time (Notes 1, 13) IO PIN: 1-Wire READ Read Low Time (Notes 1, 14) Read Sample Time (Notes 1, 14) REAL-TIME CLOCK Frequency Deviation TEMPERATURE CONVERTER Tempcore Operating Range Conversion Time Thermal Response Time Constant Conversion Error (Notes 16, 17) Number of Conversions NCONV TTC tCONV RESP F DS1921G SYMBOL CONDITIONS MIN 60 6 8.5 5 1 5 1 tRL + tRL + -48 -40 19 TYP MAX 120 15 15 15 2 15 215 2 +46 +85 90 UNITS tW0L Overdrive speed, VPUP > 4.5V Overdrive speed Standard speed Overdrive speed Standard speed Overdrive speed Standard speed Overdrive speed -5C to +46C s tW1L s tRL tMSR s s ppm C ms s (Note 15) -40C to < -30C -30C to +70C > +70C to +85C (Notes 4, 18) -1.3 -1.0 -1.3 130 +1.3 +1.0 +1.3 C -- (See the lifetime graphs.) Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: System requirement. Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2480B may be required. Capacitance on IO could be 800pF when power is first applied. If a 2.2k resistor is used to pull up the data line, 2.5s after VPUP has been applied, the parasite capacitor does not affect normal communication. These values are derived from simulation across process, voltage, and temperature and are not production tested. Input load is to ground. All voltages are referenced to ground. VTL and VTH are functions of the internal supply voltage, which is a function of VPUP and the 1-Wire recovery times. The VTH and VTL maximum specifications are valid at VPUP = 5.25V. In any case, VTL < VTH < VPUP. Voltage below which, during a falling edge of IO, a logic 0 is detected. The voltage on IO must be less than or equal to VILMAX whenever the master drives the line low. Voltage above which, during a rising edge on IO, a logic 1 is detected. The I-V characteristic is linear for voltages less than 1V. Numbers in bold are not in compliance with the published iButton standards. See the Comparison Table. in Figure 15 represents the time required for the pullup circuitry to pull the voltage on the IO pin up from VIL to VTH. The actual maximum duration for the master to pull the line low is tW1LMAX + tF - and tW0LMAX + tF - , respectively. in Figure 15 represents the time required for the pullup circuitry to pull the voltage on the IO pin up from VIL to the input high threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF. This number was derived from a test conducted by Cemagref in Antony, France, in July 2000. http://www.cemagref.fr/English/index.htm Test Report No. E42 Total accuracy is plus 0.25C quantization due to the 0.5C digital resolution of the device. _______________________________________________________________________________________ 3 Thermochron iButton DS1921G ELECTRICAL CHARACTERISTICS (continued) (VPUP = +2.8V to +5.25V, TA = -40C to +85C.) Note 17: WARNING: Not for use as the sole method of measuring or tracking temperature in products and articles that could affect the health or safety of persons, plants, animals, or other living organisms, including but not limited to foods, beverages, pharmaceuticals, medications, blood and blood products, organs, flammable, and combustible products. User shall assure that redundant (or other primary) methods of testing and determining the handling methods, quality, and fitness of the articles and products should be implemented. Temperature tracking with this product, where the health or safety of the aforementioned persons or things could be adversely affected, is only recommended when supplemental or redundant information sources are used. Data-logger products are 100% tested and calibrated at time of manufacture by Maxim to ensure that they meet all data sheet parameters, including temperature accuracy. User shall be responsible for proper use and storage of this product. As with any sensor-based product, user shall also be responsible for occasionally rechecking the temperature accuracy of the product to ensure it is still operating properly. Note 18: The number of temperature conversions (= samples) possible with the built-in energy source depends on the operating and storage temperature of the device. When not in use for a mission, the RTC oscillator should be turned off and the device should be stored at a temperature not exceeding +25C. Under this condition the shelf life time is 10 years minimum. COMPARISON TABLE LEGACY VALUES PARAMETER STANDARD SPEED (s) MIN t SLOT (including tREC) tRSTL t PDH t PDL tW0L 61 480 15 60 60 MAX (undefined) (undefined) 60 240 120 OVERDRIVE SPEED (s) MIN 7 48 2 8 6 MAX (undefined) 80 6 24 16 MIN 65* 540 15 60 60 DS1921G VALUES STANDARD SPEED (s) MAX (undefined) 640 60 270 120 OVERDRIVE SPEED (s) MIN 8* 58 1.1 7.5 8.5 MAX (undefined) 80 6 32 15 *Intentional change; longer recovery time between time slots. Note: Numbers in bold are not in compliance with the published iButton standards. iButton CAN PHYSICAL SPECIFICATION SIZE WEIGHT SAFETY See the Package Information section. Ca. 3.3g Meets UL 913, 5th Ed., Rev. 1997-02-24; Intrinsically Safe Apparatus, approval under Entity Concept for use in Class I, Division 1, Group A, B, C, and D Locations. 4 _______________________________________________________________________________________ Thermochron iButton RTC Deviation vs. Temperature 4 UPPER LIMIT 2 RTC DEVIATION (MINUTES/MONTH) DS1921G 0 LOWER LIMIT -2 -4 -6 -8 -10 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 TEMPERATURE (C) Minimum Product Lifetime vs. Temperature at Different Sample Rates 11.00 10.00 9.00 MINIMUM PRODUCT LIFETIME (YEARS) 8.00 7.00 6.00 5.00 4.00 3.00 2.00 1.00 0.00 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 EVERY MINUTE NO SAMPLES EVERY 3 MINUTES OSCILLATOR OFF EVERY 10 MINUTES TEMPERATURE (C) _______________________________________________________________________________________ 5 Thermochron iButton DS1921G Minimum Product Lifetime vs. Sample Rate at Different Temperatures 11.00 10.00 9.00 MINIMUM PRODUCT LIFETIME (YEARS) 8.00 7.00 6.00 +50C 5.00 4.00 3.00 2.00 1.00 +85C 0.00 1 10 MINUTES BETWEEN SAMPLES 100 1000 +55C +60C +15C -20C -40C +40C +45C +70C Accuracy Limits 2.0 1.5 UPPER LIMIT 1.0 0.5 ACCURACY (C) 0 -0.5 LOWER LIMIT -1.0 -1.5 -2.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 TEMPERATURE (C) 6 _______________________________________________________________________________________ Thermochron iButton Detailed Description The DS1921G Thermochron iButton is an ideal device to monitor the temperature of any object it is attached to or shipped with, such as perishable goods or containers of temperature-sensitive chemicals. The read/write NV memory can store an electronic copy of shipping information, date of manufacture and other important data written as clear as well as encrypted files. Note that the initial sealing level of the DS1921G achieves IP56. Aging and use conditions can degrade the integrity of the seal over time, therefore, for applications with significant exposure to liquids, sprays, or other similar environments, it is recommended to place the Thermochron in the DS9107 iButton capsule. The DS9107 provides a watertight enclosure that has been rated to IP68 (refer to Application Note 4126: Understanding the IP (Ingress Protection) Ratings of iButton Data Loggers and Capsule). DS1921G Overview Figure 1 shows the relationships between the major control and memory sections of the DS1921G. The device has seven main data components: 64-bit lasered ROM; 256-bit scratchpad; 4096-bit generalpurpose SRAM; 256-bit register page of timekeeping, control, and counter registers; 96 bytes of alarm timestamp and duration logging memory; 126 bytes of 1-Wire PORT IO ROM FUNCTION CONTROL 64-BIT LASERED ROM PARASITE-POWERED CIRCUITRY MEMORY FUNCTION CONTROL DS1921G 256-BIT SCRATCHPAD GENERAL-PURPOSE SRAM 32.768kHz OSCILLATOR INTERNAL TIMEKEEPING, CONTROL REGISTERS, AND COUNTERS REGISTER PAGE TEMPERATURE CORE ALARM TIMESTAMP AND DURATION LOGGING MEMORY HISTOGRAM MEMORY CONTROL LOGIC DATA-LOG MEMORY 3V LITHIUM Figure 1. Block Diagram _______________________________________________________________________________________ 7 Thermochron iButton histogram memory; and 2048 bytes of data-logging memory. Except for the ROM and the scratchpad, all other memory is arranged in a single linear address space. All memory reserved for logging purposes, including counter registers and several other registers, is read-only for the user. The timekeeping and control registers are write protected while the device is programmed for a mission. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one of the seven ROM function commands: Read ROM, Match ROM, Search ROM, Conditional Search ROM, Skip ROM, Overdrive-Skip ROM, or Overdrive-Match ROM. Upon completion of an Overdrive ROM command byte executed at standard speed, the device enters overdrive mode, where all subsequent communication occurs at a higher speed. The protocol required for these ROM function commands is described in Figure 13. After a ROM function command is successfully executed, the memory functions become accessible and the master can provide any one of the seven DS1921G available commands. The protocol for these memory function commands is described in Figure 10. All data is read and written least significant bit first. Parasite Power Figure 1 shows the parasite-powered circuitry. This circuitry "steals" power whenever the IO input is high. IO provides sufficient power as long as the specified timing and voltage requirements are met. The advantages of parasite power are two-fold: 1) By parasiting off this input, battery power is not consumed for 1-Wire ROM function commands, and 2) if the battery is exhausted for any reason, the ROM may still be read normally. The remaining circuitry of the DS1921G is solely operated by battery energy. 64-Bit Lasered ROM Each DS1921G contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a cyclic redundancy check (CRC) of the first 56 bits (see Figure 3 for details). The 1-Wire CRC is generated BUS MASTER 1-Wire NET OTHER DEVICES DS1921G COMMAND LEVEL: AVAILABLE COMMANDS: READ ROM MATCH ROM SEARCH ROM SKIP ROM OVERDRIVE-SKIP ROM OVERDRIVE-MATCH ROM CONDITIONAL SEARCH ROM COMMAND CODES: 33h 55h F0h CCh 3Ch 69h ECh DATA FIELD AFFECTED: 64-BIT ROM 64-BIT ROM 64-BIT ROM N/A OD-FLAG 64-BIT ROM, OD-FLAG 64-BIT ROM, CONDITIONAL SEARCH SETTINGS, DEVICE STATUS 256-BIT SCRATCHPAD, FLAGS 256-BIT SCRATCHPAD 4096-BIT SRAM, REGISTERS, FLAGS ALL MEMORY ALL MEMORY MISSION TIMESTAMP, MISSION SAMPLES COUNTER, START DELAY, SAMPLE RATE, ALARM TIMESTAMPS AND DURATIONS, HISTOGRAM MEMORY MEMORY ADDRESS 211h 1-Wire ROM FUNCTION COMMANDS DS1921G-SPECIFIC MEMORY/CONTROL FUNCTION COMMANDS WRITE SCRATCHPAD READ SCRATCHPAD COPY SCRATCHPAD READ MEMORY READ MEMORY WTH CRC CLEAR MEMORY 0Fh AAh 55h F0h A5h 3Ch CONVERT TEMPERATURE 44h Figure 2. Hierarchical Structure for 1-Wire Protocol 8 _______________________________________________________________________________________ Thermochron iButton DS1921G MSB 8-BIT CRC CODE MSB LSB MSB 48-BIT SERIAL NUMBER LSB MSB 8-BIT FAMILY CODE (21h) LSB LSB Figure 3. 64-Bit Lasered ROM POLYNOMIAL = X8 + X5 + X4 + 1 1ST STAGE X0 X1 2ND STAGE X2 3RD STAGE X3 4TH STAGE X4 5TH STAGE X5 6TH STAGE X6 7TH STAGE X7 8TH STAGE X8 INPUT DATA Figure 4. 1-Wire CRC Generator using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the 1-Wire CRC is available in Application Note 27: Understanding and Using Cyclic Redundancy Checks with Maxim iButton Products. The Shift register bits are initialized to 0. Then, starting with the least significant bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, the serial number is then entered. After the 48th bit of the serial number has been entered, the Shift register contains the CRC value. Shifting in the 8 bits of CRC returns the Shift register to all zeros. Memory Figure 5 shows the DS1921G memory map. The 4096bit general-purpose SRAM makes up pages 0 to 15. The timekeeping, control, and counter registers fill page 16, called register page (see Figure 6). Pages 17, 18, and 19 are assigned to storing the alarm timestamps and durations. The temperature histogram bins begin at page 64 and use up to four pages. The temperature-logging memory covers pages 128 to 191. Memory pages 20 to 63, 68 to 127, and 192 to 255 are reserved for future extensions. The scratchpad is an additional page that acts as a buffer when writing to the SRAM memory or the register page. The memory pages 17 and higher are read only for the user. They are written to or erased solely under the supervision of the on-chip control logic. _______________________________________________________________________________________ 9 Thermochron iButton DS1921G 32-BYTE INTERMEDIATE STORAGE SCRATCHPAD ADDRESS 0000h to 01FFh 0200h to 021Fh 0220h to 027Fh 0280h to 07FFh 0800h to 087Fh 0880h to 0FFFh 1000h to 17FFh 1800h to 1FFFh GENERAL-PURPOSE SRAM (16 PAGES) 32-BYTE REGISTER PAGE ALARM TIMESTAMPS AND DURATIONS (RESERVED FOR FUTURE EXTENSIONS) TEMPERATURE HISTOGRAM MEMORY (RESERVED FOR FUTURE EXTENSIONS) DATA-LOG MEMORY (64 PAGES) (RESERVED FOR FUTURE EXTENSIONS) PAGES 0 to 15 PAGE 16 PAGES 17 to 19 PAGES 20 to 63 PAGES 64 to 67 PAGES 68 to 127 PAGES128 to 191 PAGES 192 to 255 Figure 5. Memory Map ADDRESS 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020Ah 020Bh 020Ch 020Dh 020Eh 020Fh BIT 7 0 0 0 0 0 CENT BIT 6 BIT 5 10 Seconds 10 Minutes 20 Hour AM/PM 0 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION ACCESS* Single Seconds Single Minutes 10 Hour 0 0 Single Hours Day of Week Single Date Single Months Single Years Single Seconds Alarm Single Minutes Alarm Single Hours Alarm 0 Day of Week Alarm Temperature Alarms Sample Rate TAS Control -- THS R/W R/W R/W R R/W** R** R/W** R** RTC Alarm Registers R/W R/W** RTC Registers R/W R/W** 12/24 0 0 0 10 Date 0 10 Years 10 Months MS MM MH MD 10 Seconds Alarm 10 Minutes Alarm 12/24 0 20 Hour AM/PM Alarm 0 10 Hour Alarm 0 Temperature Low Alarm Threshold Temperature High Alarm Threshold Number of Minutes Between Temperature Conversions EOSC EMCLR 0 EM RO TLS (No function, reads 00h) *The left entry in the ACCESS column is valid between missions. The right entry shows the applicable access mode while a mission is in progress. **While a mission is in progress, these addresses can be read. The first attempt to write to these registers (even read-only ones), however, ends the mission and overwrites selected writable registers. Figure 6. Register Pages Map 10 ______________________________________________________________________________________ Thermochron iButton DS1921G ADDRESS 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021Ah 021Bh 021Ch 021Dh 021Eh 021Fh TCB MEMCLR MIP BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION -- Temperature Mission Start Delay TLF THF TAF Status ACCESS* R R R/W R/W R** R** R/W** R/W (No function, reads 00h) Temperature Read-Out (Forced Conversion) Low Byte High Byte SIP Minutes Hours Date Month Year Low Byte Center Byte High Byte Low Byte Center Byte High Byte Mission Samples Counter Device Samples Counter R R Mission Timestamp R R 0 R R *The left entry in the ACCESS column is valid between missions. The right entry shows the applicable access mode while a mission is in progress. **While a mission is in progress, these addresses can be read. The first attempt to write to these registers (even read-only ones), however, ends the mission and overwrites selected writable registers. Figure 6. Register Pages Map (continued) Detailed Register Descriptions Timekeeping The RTC/alarm and calendar information is accessed by reading/writing the appropriate bytes in the register page, address 0200h to 0206h. Note that some bits are set to 0. These bits always read 0 regardless of how they are written. The contents of the time, calendar, and alarm registers are in the binary-coded decimal (BCD) format. RTC/Calendar The RTC of the DS1921G can run in either 12hr or 24hr mode. Bit 6 of the Hours register (address 0202h) is defined as the 12hr or 24hr mode select bit. When high, the 12hr mode is selected. In the 12hr mode, bit 5 is the AM/PM bit with logic 1 being PM. In the 24hr mode, bit 5 is the 20hr bit (20hr to 23hr). To distinguish between the days of the week, the DS1921G includes a counter with a range from 1 to 7. The assignment of a counter value to the day of week is arbitrary. Typically, the number 1 is assigned to a Sunday (U.S. standard) or to a Monday (European standard). The calendar logic is designed to automatically compensate for leap years. For every year value that is either 00 or a multiple of four, the device adds a 29th of February. This works correctly up to (but not including) the year 2100. The DS1921G is Y2K compliant. Bit 7 (CENT) of the Months register at address 0205h serves as a century flag. When the Year register rolls over from 99 to 00, the century flag toggles. It is recommended to write the century bit to a 1 when setting the RTC to a time/date between the years 2000 and 2099. ______________________________________________________________________________________ 11 Thermochron iButton DS1921G RTC and RTC Alarm Registers Map ADDRESS 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020Ah MS MM MH MD 12/24 0 BIT 7 0 0 0 0 0 CENT 12/24 0 0 0 10 Years 10 Seconds Alarm 10 Minutes Alarm 20 Hour AM/PM Alarm 0 10 Hour Alarm 0 0 0 BIT 6 BIT 5 10 Seconds 10 Minutes 20 Hour AM/PM 0 10 Date 10 Months 10 Hour 0 0 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Single Seconds Single Minutes Single Hours Day of Week Single Date Single Months Single Years Single Seconds Alarm Single Minutes Alarm Single Hours Alarm Day of Week Alarm RTC Alarm Control ALARM REGISTER MASK BITS (BIT 7 OF 0207h TO 20Ah) MS 1 0 0 0 0 MM 1 1 0 0 0 MH 1 1 1 0 0 MD 1 1 1 1 0 Alarm once per second. Alarm when seconds match (once per minute). Alarm when minutes and seconds match (once every hour). Alarm when hours, minutes, and seconds match (once every day). Alarm when day, hours, minutes, and seconds match (once every week). FUNCTION RTC Alarms The DS1921G also contains an RTC alarm function. The RTC Alarm registers are located in registers 0207h to 020Ah. The most significant bit of each of the alarm registers is a mask bit. When all the mask bits are logic 0, an alarm occurs once per week when the values stored in timekeeping registers 0200h to 0203h match the values stored in the RTC Alarm registers. Any alarm sets the timer alarm flag (TAF) in the device's Status register (address 214h). The bus master can set the search conditions in the Control register (address 20Eh) to identify devices with timer alarms by means of the conditional search function (see the ROM Function Commands section). 12 ______________________________________________________________________________________ Thermochron iButton Temperature Alarm Register Map ADDRESS 020Bh 020Ch BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Temperature Low Alarm Threshold Temperature High Alarm Threshold DS1921G Sample Rate Register Map ADDRRESS 020Dh BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Sample Rate Temperature Conversion The DS1921G measures temperatures with a resolution of 0.5C. Temperature values are represented in a single byte as an unsigned binary number, which translates into a theoretical range of 128C. The range, however, has been limited to values from 0000 0000 (00h) through 1111 1010 (FAh). The codes 01h to F9h are considered valid temperature readings. If a temperature conversion yields a temperature that is out of range, it is recorded as 00h (if too low) or FAh (if too high). Since out-of-range results are accumulated in histogram bins 0 and 62 (see the Temperature Logging and Histogram section), the data in these bins is of limited value. For this reason the specified temperature range of the DS1921G is considered to begin at code 04h and end at code F7h, which corresponds to histogram bins 1 to 61. With T[7...0] representing the decimal equivalent of a temperature reading, the temperature value is calculated as (C) = T[7...0]/2 - 40.0 This equation is valid for converting temperature readings stored in the data-log memory as well as for data read from the Forced Temperature Conversion Readout register (address 0211h). To specify the temperature alarm thresholds, this equation needs to be resolved to T[7...0] = 2 x (C) + 80.0 A value of 23C, for example, thus translates into 126 decimal or 7Eh. This corresponds to the binary patterns 0111 1110, which could be written to a Temperature Alarm register (address 020Bh and 020Ch, respectively). Sample Rate The content of the Sample Rate register (address 020Dh) determines how many minutes the temperature conversions are apart from each other during a mission. The sample rate can be any value from 1 to 255, coded as an unsigned 8-bit binary number. If the memory has been cleared (Status register bit MEMCLR = 1) and a mission is enabled (Control register bit EM = 0), writing a nonzero value to the Sample Rate register starts a mission. For a full description of the correct sequence of steps to start a temperature-logging mission, see the Missioning or Mission Example: Prepare and Start a New Mission sections. ______________________________________________________________________________________ 13 Thermochron iButton DS1921G Control Register Map ADDRESS 020Eh BIT 7 EOSC BIT 6 EMCLR BIT 5 0 BIT 4 EM BIT 3 RO BIT 2 TLS BIT 1 THS BIT 0 TAS Control Register The DS1921G is set up for its operation by writing appropriate data to its special function registers that are located in the register page. Several functions that are controlled by a single bit only are combined into a single byte called the Control register (address 020Eh). This register can be read and written. If the device is programmed for a mission, writing to the Control register ends the mission and changes the register contents. The functional assignments of the individual bits are explained below. Bit 5 has no function. It always reads 0 and cannot be written to 1. Bit 7: Enable Oscillator (EOSC). This bit controls the crystal oscillator of the RTC. When set to logic 0, the oscillator starts operation. When written to logic 1, the oscillator stops and the device is in a low-power dataretention mode. This bit must be 0 for normal operation. The RTC must have advanced at least 1 second before a Mission Start is accepted. Bit 6: Memory Clear Enable (EMCLR). This bit needs to be set to logic 1 to enable the Clear Memory function, which is invoked as a memory function command. The timestamp, histogram memory as well as the Mission Timestamp, Mission Samples Counter, Mission Start Delay, and Sample Rate are cleared only if the Clear Memory command is issued with the next access to the device. The EMCLR bit returns to 0 as the next memory function command is executed. Bit 4: Enable Mission (EM). This bit controls whether the DS1921G begins a mission as soon as the sample rate is written. To enable the device for a mission, this bit must be 0. Bit 3: Rollover Enable/Disable (RO). This bit controls whether the temperature logging memory is overwritten with new data or whether data logging is stopped once the memory is filled with data during a mission. Setting this bit to a 1 enables the rollover and data logging continues at the beginning, overwriting previously collected data. Clearing this bit to 0 disables the rollover and no further temperature values are stored in the temperature logging memory once it is filled with data. This does not stop the mission. The device continues measuring temperatures and updating the histogram and alarm timestamps and durations. Bit 2: Temperature Low Alarm Search (TLS). If this bit is 1, the device responds to a Conditional Search ROM command if, during a mission, the temperature has reached or is lower than the Low Temperature Threshold stored at address 020Bh. Bit 1: Temperature High Alarm Search (THS). If this bit is 1, the device responds to a Conditional Search ROM command if, during a mission, the temperature has reached or is higher than the High Temperature Threshold stored at address 020Ch. Bit 0: Timer Alarm Search (TAS). If this bit is 1, the device responds to a Conditional Search ROM command if, during a mission, a timer alarm has occurred. Since a timer alarm cannot be disabled, the TAF flag usually reads 1 during a mission. Therefore, it is advisable to set the TAS bit to a 0, in most cases. Mission Start Delay Counter The content of the Mission Start Delay Counter register determines how many minutes the device waits before starting the logging process. The Mission Start Delay value is stored as an unsigned 16-bit integer number at addresses 0212h (low byte) and 0213h (high byte). The maximum delay is 65,535 minutes, equivalent to 45 days, 12 hours, and 15 minutes. For a typical mission, the Mission Start Delay is 0. If a mission is too long for a single DS1921G to store all temperature readings at the selected sample rate, one can use several devices, staggering the Mission Start Delay to record the full period. In this case, the rollover enable (RO) bit in the Control register (address 020Eh) must be set to 0 to prevent overwriting of the recorded temperature log after the data-log memory is full. See the Mission Start and Logging Process section and Figure 11 for details. 14 ______________________________________________________________________________________ Thermochron iButton Status Register Map ADDRESS 0214h BIT 7 TCB BIT 6 MEMCLR BIT 5 MIP BIT 4 SIP BIT 3 0 BIT 2 TLF BIT 1 THF BIT 0 TAF DS1921G Status Register The Status register holds device status information and alarm flags. The register is located at address 0214h. Writing to this register does not necessarily end a mission. The functional assignments of the individual bits are explained below. The bits MIP, TLF, THF, and TAF can only be written to 0. All other bits are read-only. Bit 3 has no function. Bit 7: Temperature Core Busy (TCB). If this bit reads 0, the DS1921G is currently performing a temperature conversion. This temperature conversion is either selfinitiated because of a mission being in progress or initiated by a command when a mission is not in progress. The TCB bit goes low just before a conversion starts and returns to high just after the result is latched into the Read-Out register at address 0211h. Bit 6: Memory Cleared (MEMCLR). If this bit reads 1, the memory pages 17 and higher (alarm timestamps/ durations, temperature histogram, excluding data-log memory), as well as the Mission Timestamp, Mission Samples Counter, Mission Start Delay, and Sample Rate have been cleared to 0 from executing a Clear Memory function command. The MEMCLR bit returns to 0 as soon as writing a nonzero value to the Sample Rate register starts a new mission, provided that the EM bit is also 0. The memory has to be cleared in order for a mission to start. Bit 5: Mission in Progress (MIP). If this bit reads 1, the DS1921G has been set up for a mission and this mission is still in progress. A mission is started if the EM bit of the Control register (address 20Eh) is 0 and a nonzero value is written to the Sample Rate register, address 20Dh. The MIP bit returns from logic 1 to logic 0 when a mission is ended. A mission ends with the first write attempt (Copy Scratchpad command) to any register in the address range of 200h to 213h. Alternatively, a mission can be ended by directly writing to the Status register and setting the MIP bit to 0. The MIP bit cannot be set to 1 by writing to the Status register. BIT 4: Sample in Progress (SIP). If this bit reads 1, the DS1921G is currently performing a temperature conversion as part of a mission in progress. The mission samples occur on the seconds rollover from 59 to 00. The SIP bit changes from 0 to 1 approximately 250ms before the actual temperature conversion begins allowing the circuitry of the chip to wake up. A temperature conversion including a wake-up phase takes maximum 875ms. During this time, read accesses to the memory pages 17 and higher are permissible but can reveal invalid data. Bit 2: Temperature Low Flag (TLF). Logic 1 in the temperature low flag bit indicates that a temperature measurement during a mission revealed a temperature equal to or lower than the value in the Temperature Low Threshold register. The temperature low flag can be cleared at any time by writing this bit to 0. This flag must be cleared before starting a new mission. Bit 1: Temperature High Flag (THF). Logic 1 in the temperature high flag bit indicates that a temperature measurement during a mission revealed a temperature equal to or higher than the value in the Temperature High Threshold register. The temperature high flag can be cleared at any time by writing this bit to 0. This flag must be cleared before starting a new mission. Bit 0: Timer Alarm Flag (TAF). If this bit reads 1, a RTC alarm has occurred (see the Timekeeping section for details). The timer alarm flag can be cleared at any time by writing this bit to logic 0. Since the timer alarm cannot be disabled, the TAF flag usually reads 1 during a mission. This flag should be cleared before starting a new mission. ______________________________________________________________________________________ 15 Thermochron iButton DS1921G Mission Timestamp Register Map ADDRESS 0215h 0216h 0217h 0218h 0219h BIT 7 0 0 0 0 12/24 0 0 10 Years 0 BIT 6 BIT 5 10 Minutes 20 Hour AM/PM 10 Hour BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Single Minutes Single Hours Single Date Single Months Single Years 10 Date 10 Months Mission Samples Counter Register Map ADDRESS 021Ah 021Bh 021Ch BIT 7 BIT 6 BIT 5 BIT 4 Low Byte Center Byte High Byte BIT 3 BIT 2 BIT 1 BIT 0 Device Samples Counter Register Map ADDRESS 021Dh 021Eh 021Fh BIT 7 BIT 6 BIT 5 BIT 4 Low Byte Center Byte High Byte BIT 3 BIT 2 BIT 1 BIT 0 Mission Timestamp The Mission Timestamp register indicates the time and date of the first temperature conversion of a mission. Subsequent temperature conversions take place as many minutes apart from each other as specified by the value in the Sample Rate register. Mission samples occur on minute boundaries. Temperature Logging and Histogram Once set up for a mission, the DS1921G logs the temperature measurements simultaneously byte after byte in the data-log memory as well as in histogram form in the histogram memory. The data-log memory is able to store 2,048 temperature values measured at equidistant time points. The first temperature value of a mission is written to address location 1000h of the data-log memory, the second value to address location 1001h and so on. Knowing the starting time point (Mission Timestamp register), the interval between temperature measurements, the Mission Samples Counter register, and the rollover setting, one can reconstruct the time and date of each measurement stored in the data log. There are two alternatives to the way the DS1921G behaves after the 2048 bytes of data-log memory is filled with data. With rollover disabled (RO = 0), the device fills the data-log memory with the first 2048 mission samples. Additional mission samples are not logged in the data-log, but the histogram and temperature alarm RAM continue to update. With rollover enabled (RO = 1), the data log wraps around and overwrites previous data starting at 1000h for the every 2049th mission sample. In this mode, the device stores the last 2048 mission samples. Mission Samples Counter The Mission Samples Counter register indicates how many temperature measurements have taken place during the current mission in progress (if MIP = 1) or during the latest mission (if MIP = 0). The value is stored as an unsigned 24-bit integer number. This counter is reset through the Clear Memory command. Device Samples Counter The Device Samples Counter register indicates how many temperature measurements have taken place since the device was assembled at the factory. The value is stored as an unsigned, 24-bit integer number. The maximum number that can be represented in this format is 16,777,215, which is higher than the expected lifetime of the DS1921G iButton. This counter cannot be reset under software control. 16 ______________________________________________________________________________________ Thermochron iButton DS1921G TEMPERATURE READING 00h 01h 02h 03h 04h 05h 06h 07h 08h ... F3h F4h F5h F6h F7h F8h F9h FAh TEMPERATURE EQUIVALENT IN C -40.0 or lower -39.5 -39.0 -38.5 -38.0 -37.5 -37.0 -36.5 -36.0 ... +81.5 +82.0 +82.5 +83.0 +83.5 +84.0 +84.5 +85.0 or higher HISTOGRAM BIN NUMBER 0 0 0 0 1 1 1 1 2 ... 60 61 61 61 61 62 62 62 HISTOGRAM BIN ADDRESS 800h to 801h 800h to 801h 800h to 801h 800h to 801h 802h to 803h 802h to 803h 802h to 803h 802h to 803h 804h to 805h ... 878h to 879h 87Ah to 87Bh 87Ah to 87Bh 87Ah to 87Bh 87Ah to 87Bh 87Ch to 87Dh 87Ch to 87Dh 87Ch to 87Dh Figure 7. Histogram Bin and Temperature Cross-Reference For the temperature histogram, the DS1921G provides 63 bins that begin at memory address 0800h. Each bin consists of a 16-bit, nonrolling-over binary counter that is incremented each time a temperature value acquired during a mission falls into the range of the bin. The least significant byte of each bin is stored at the lower address. Bin 0 begins at memory address 0800h, bin 1 at 0802h, and so on up to 087Ch for bin 62, as shown in Figure 7. The number of the bin to be updated after a temperature conversion is determined by cutting off the two least significant bits of the binary temperature value. Out-of-range values are range locked and counted as 00h or FAh. Since each data bin is 2 bytes, it can increment up to 65,535 times. Additional measurements for a bin that has already reached its maximum value are not counted; the bin counter remains at its maximum value. With the fastest sample rate of one sample every minute, a 2-byte bin is sufficient for up to 45 days if all temperature readings fall into the same bin. Temperature Alarm Logging For some applications it is essential to not only record temperature over time and the temperature histogram, but also record when exactly the temperature exceeded a predefined tolerance band and for how long the temperature stayed outside the desirable range. The DS1921G can log high and low durations. The tolerance band is specified by means of the Temperature Alarm Threshold registers, addresses 20Bh and 20Ch in the register page. One can set a high temperature and low temperature threshold. See the Temperature Conversion section for the data format the temperature has to be written in. As long as the temperature values stay within the tolerance band (i.e., are higher than the low threshold and lower than the high threshold), the DS1921G does not record any temperature alarm. If the temperature during a mission reaches or exceeds either threshold, the DS1921G generates an alarm and sets either the temperature high flag (THF) or the temperature low flag (TLF) in the Status register (address ______________________________________________________________________________________ 17 Thermochron iButton DS1921G ADDRESS 0220h 0221h 0222h 0223h 0224h to 0227h 0228h to 024Fh 0250h 0251h 0252h 0253h 0254h to 0257h 0258h to 027Fh DESCRIPTION Mission Samples Counter, Low Byte Mission Samples Counter, Center Byte Mission Samples Counter, High Byte Alarm Duration Counter Alarm Timestamp and Duration Alarm Timestamp and Durations Mission Samples Counter, Low Byte Mission Samples Counter, Center Byte Mission Samples Counter, High Byte Alarm Duration Counter Alarm Timestamp and Duration Alarm Timestamp and Durations High Alarm 2 High Alarms 3 to 12 High Alarm 1 Low Alarm 2 Low Alarms 3 to 12 Low Alarm 1 ALARM EVENT Figure 8. Alarm Timestamps and Durations Address Map 214h). This way, if the search conditions (address 20Eh) are set accordingly, the master can quickly identify devices with temperature alarms by means of the conditional search function (see the ROM Function Commands section). The device also generates a timestamp of when the alarm occurred and begins recording the duration of the alarming temperature. Timestamps and durations where the temperature leaves the tolerance band are stored in the address range 0220h to 027Fh, as shown in Figure 8. This allocation allows recording 24 individual alarm events and periods (12 periods for too hot and 12 for too cold). The date and time of each of these periods can be determined from the Mission Timestamp register and the time distance between each temperature reading. The alarm timestamp is a copy of the Mission Samples Counter register when the alarm first occurred. The least significant byte is stored at the lower address. One address higher than the timestamp, the DS1921G maintains a 1-byte duration counter that stores the number of samples the temperature was found to be beyond the threshold. If this counter has reached its limit after 255 consecutive temperature readings and the temperature has not yet returned to within the tolerance band, the device issues another timestamp at the next higher alarm location and opens another counter to record the duration. If the temperature returns to normal before the counter has reached its limit, the dura- tion counter of the particular timestamp does not increment any further. Should the temperature again cross this threshold, it is recorded at the next available alarm location. This algorithm is implemented for the low temperature thresholds as well as for the high temperature threshold. Missioning The typical task of the DS1921G iButton is recording the temperature of a temperature-sensitive object. Before the device can perform this function, it needs to be configured. This procedure is called missioning. First, the DS1921G must have its RTC set to a valid time and date. This reference time can be UTC (also called GMT, Greenwich Mean Time) or any other time standard that was chosen for the application. The clock must be running (EOSC = 0) for at least one second. Setting an RTC alarm is optional. The memory assigned to store the alarm timestamps and durations, temperature histogram, Mission Timestamp, Mission Samples Counter, Mission Start Delay, and Sample Rate must be cleared using the Clear Memory command. In case there were temperature alarms in the previous mission, the TLF and THF flags need to be cleared manually. To enable the device for a mission, the EM flag must be set to 0. These are general settings that have to be made regardless of the type of object to be monitored and the duration of the mission. 18 ______________________________________________________________________________________ Thermochron iButton Next, the low temperature and high temperature thresholds that specify the temperature tolerance band must be defined. The Temperature Conversion section describes how to convert a temperature value into the binary code to be written to the threshold registers. The state of the search condition bits in the Control register does not affect the mission. If multiple devices are connected to form a 1-Wire net, the setting of the search condition enables these devices to participate in the conditional search if certain events, such as timer or temperature alarms, have occurred. Details on the search conditions are found in the ROM Function Commands section and in the Control register description. The setting of the rollover-enable bit (RO) and sample rate depends on the duration of the mission and the monitoring requirements. If the most recent temperature history is important, the rollover should be enabled (RO = 1). Otherwise, one should estimate the duration of the mission in minutes and divide the number by 2048 to calculate the value of the sample rate (number of minutes between temperature conversions). For example, if the estimated duration of a mission is 10 days (14,400min), then the 2048-byte capacity of the data-log memory would be sufficient to store a new value every 7min. If the DS1921G's data-log memory is not large enough to store all temperature readings, one can use several devices and set the Mission Start Delay to values that make the second device start recording as soon as the memory of the first device is full and so on. The RO bit needs to be set to 0 to disable rollover that would otherwise overwrite the recorded temperature log. After the RO bit and the Mission Start Delay are set, the Sample Rate register is the last element of data that is written. The sample rate can be any value from 1 to 255, coded as an unsigned 8-bit binary number. As soon as the sample rate is written, the DS1921G sets the MIP flag and clears the MEMCLR flag. After as many minutes as specified by the Mission Start Delay are over, the device waits for the next minute boundary, then wakes up, copies the current time and date to the Mission Timestamp register, and makes the first temperature conversion of the mission. This increments both the Mission Samples Counter and Device Samples Counter. All subsequent temperature measurements are taken on minute boundaries specified by the value in the Sample Rate register. One can read the memory of the DS1921G to watch the mission as it progresses. Care should be taken to avoid memory access conflicts. See the Memory Access Conflicts section for details. Address Registers and Transfer Status Because of the serial data transfer, the DS1921G employs three address registers, called TA1, TA2, and E/S (Figure 9). Registers TA1 and TA2 must be loaded with the target address to which the data is written or from which data is sent to the master upon a read command. Register E/S acts like a byte counter and transfer status register. It is used to verify data integrity with write commands. Therefore, the master has only read access to this register. The lower 5 bits of the E/S register indicate the address of the last byte that has been written to the scratchpad. This address is called Ending Offset. Bit 5 of the E/S register, called PF or partial byte flag, is set if the number of data bits sent by the master is not an integer multiple of 8. Bit 6 is always a 0. Note that the lowest 5 bits of the target address also determine the address within the scratchpad where intermediate storage of data begins. This address is called byte offset. If the target address for a write command is 13Ch, for example, then the scratchpad stores incoming data beginning at the byte offset 1Ch and is full after only 4 bytes. The corresponding ending offset in this example is 1Fh. For the best economy of speed and efficiency, the target address for writing should point to the beginning of a new page, i.e., the byte offset is 0. Thus, the full 32-byte capacity of the scratchpad is available, resulting also in the ending offset of 1Fh. However, it is possible to write one or several contiguous bytes somewhere within a page. The ending offset together with the partial and overflow flag are a means to support the master checking the data integrity after a write command. The highest valued bit of the E/S register, called authorization accepted (AA), indicates that a valid copy command for the scratchpad has been received and executed. Writing data to the scratchpad clears this flag. DS1921G Writing with Verification To write data to the DS1921G, the scratchpad must be used as intermediate storage. First, the master issues the Write Scratchpad command to specify the desired target address, followed by the data to be written to the scratchpad. In the next step, the master sends the Read Scratchpad command to read the scratchpad and to verify data integrity. As preamble to the scratchpad data, the DS1921G sends the requested target address TA1 and TA2 and the contents of the E/S register. If the PF flag is set, data did not arrive correctly in the scratchpad. The master does not need to continue reading; it can start a new trial to write data to the scratchpad. Similarly, a set AA flag indicates that the 19 ______________________________________________________________________________________ Thermochron iButton DS1921G BIT NUMBER TARGET ADDRESS (TA1) 7 T7 6 T6 5 T5 4 T4 3 T3 2 T2 1 T1 0 T0 TARGET ADDRESS (TA2) T15 T14 T13 T12 T11 T10 T9 T8 ENDING ADDRESS WITH DATA STATUS (E/S) (READ-ONLY) AA 0 PF E4 E3 E2 E1 E0 Figure 9. Address Registers write command was not recognized by the device. If everything went correctly, both flags are cleared and the ending offset indicates the address of the last byte written to the scratchpad. Now the master can continue verifying every data bit. After the master has verified the data, it has to send the Copy Scratchpad command. This command must be followed exactly by the data of the three address registers TA1, TA2, and E/S as the master has read them verifying the scratchpad. As soon as the DS1921G has received these bytes, it copies the data to the requested location beginning at the target address. Write Scratchpad [0Fh] After issuing the Write Scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad. The data is written to the scratchpad starting at the byte offset T[4:0]. The ending offset E[4:0] is the byte offset at which the master stops writing data. Only full data bytes are accepted. If the last data byte is incomplete, its content is ignored and the partial byte flag (PF) is set. When executing the Write Scratchpad command, the CRC generator inside the DS1921G (see Figure 16) calculates a CRC of the entire data stream, starting at the command code and ending at the last data byte sent by the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC generator and then shifting in the command code (0Fh) of the Write Scratchpad command, the target addresses TA1 and TA2 as supplied by the master, and all the data bytes. The master can end the Write Scratchpad command at any time. However, if the ending offset is 11111b, the master can send 16 read time slots and receive an inverted CRC-16 generated by the DS1921G. Note: The range 200h to 213h of the register page is protected during a mission. See Figure 6 for the access type of the individual registers between and during missions. Memory/Control Function Commands The Memory/Control Function Flowchart (Figure 10) describes the protocols necessary for accessing the memory and the special function registers of the DS1921G. An example on how to use these and other functions to set up the DS1921G for a mission is included in the Mission Example: Prepare and Start a New Mission section. The communication between master and DS1921G takes place either at standard speed (default, OD = 0) or at overdrive speed (OD = 1). If not explicitly set into the overdrive mode, the DS1921G assumes standard speed. Internal memory access during a mission has priority over external access through the 1-Wire interface. This affects the read memory commands described below. See the Memory Access Conflicts section for details. 20 ______________________________________________________________________________________ Thermochron iButton Read Scratchpad [AAh] This command is used to verify scratchpad data and target addresses. After issuing the Read Scratchpad command, the master begins reading. The first 2 bytes are the target address. The next byte is the ending offset/data status byte (E/S) followed by the scratchpad data beginning at the byte offset T[4:0], as shown in Figure 9. Regardless of the actual ending offset, the master can read data until the end of the scratchpad after which it receives an inverted CRC-16 of the command code, target addresses TA1 and TA2, the E/S byte, and the scratchpad data starting at the target address. After the CRC is read, the bus master reads logical "1"s from the DS1921G until a reset pulse is issued. The data to be copied is determined by the three address registers. The scratchpad data from the beginning offset through the ending offset is copied, starting at the target address. Anywhere from 1 to 32 bytes can be copied to memory with this command. The AA flag remains at logic 1 until it is cleared by the next Write Scratchpad command. Note that the Copy Scratchpad command, when applied to the address range 200h to 213h during a mission, ends the mission. DS1921G Read Memory [F0h] The Read Memory command can be used to read the entire memory. After issuing the command, the master must provide the 2-byte target address. After the 2 bytes, the master reads data beginning from the target address and can continue until the end of memory, at which point logic "0"s are read. It is important to realize that the target address registers contain the address provided. The ending offset/data status byte is unaffected. The hardware of the DS1921G provides a means to accomplish error-free writing to the memory section. To safeguard data in the 1-Wire environment when reading and to simultaneously speed up data transfers, it is recommended to packetize data into data packets of the size of one memory page each. Such a packet would typically store a 16-bit CRC with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to verify if the received data is correct (refer to Application Note 114: 1-Wire File Structure for the recommended file structure). Copy Scratchpad [55h] This command is used to copy data from the scratchpad to the writable memory sections. Applying a Copy Scratchpad command to the Sample Rate register can start a mission provided that several preconditions are met. See the Mission Start and Logging Process section and the flowchart in Figure 11 for details. After issuing the Copy Scratchpad command, the master must provide a 3-byte authorization pattern, which can be obtained by reading the scratchpad for verification. This pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that order). If the pattern matches, the AA flag is set and the copy begins. A pattern of alternating "1"s and "0"s is transmitted after the data has been copied until the master issues a reset pulse. While the copy is in progress, any attempt to reset the part is ignored. Copy typically takes 2s per byte. ______________________________________________________________________________________ 21 Thermochron iButton DS1921G MASTER Tx MEMORY OR CONTROL FUNCTION COMMAND FROM ROM FUNCTIONS FLOWCHART (FIGURE 13) 0Fh WRITE SCRATCHPAD? Y DS1921G SETS EMCLR = 0 N AAh READ SCRATCHPAD? Y DS1921G SETS EMCLR = 0 N 55h COPY SCRATCHPAD Y DS1921G SETS EMCLR = 0 N TO FIGURE 10b MASTER Tx TA1 [T7:T0], TA2 [T15:T8] MASTER Rx TA1 [T7:T0], TA2 [T15:T8] MASTER Tx TA1 [T7:T0], TA2 [T15:T8] DS1921G SETS SCRATCHPAD OFFSET = [T4:T0] AND CLEARS (PF, AA) MASTER Rx ENDING OFFSET WITH DATA STATUS (E/S) MASTER Tx E/S BYTE MASTER Tx DATA BYTE TO SCRATCHPAD OFFSET DS1921G SETS SCRATCHPAD OFFSET = [T4:T0] AUTHORIZATION CODE MATCH? Y N DS1921G INCREMENTS SCRATCHPAD OFFSET DS1921G SETS [E4:E0] = SCRATCHPAD OFFSET DS1921G INCREMENTS SCRATCHPAD OFFSET Y MASTER Rx DATA BYTE FROM SCRATCHPAD OFFSET AA = 1 MASTER Tx RESET? N MASTER Tx RESET? N Y DS1921G COPIES SCRATCHPAD DATA TO MEMORY MASTER Rx "1"s N COPYING FINISHED Y MASTER Rx "1"s N SCRATCHPAD OFFSET = 11111b? Y PARTIAL BYTE WRITTEN? N Y N SCRATCHPAD OFFSET = 11111b? Y MASTER Tx RESET? Y N DS1921G Tx "0" MASTER Rx CRC-16 OF COMMAND, ADDRESS, DATA, E/S BYTE, AND DATA STARTING AT THE TARGET ADDRESS MASTER Tx RESET? PF = 1 N MASTER Tx RESET? DS1921G Tx "1" N Y MASTER Tx RESET? N MASTER Rx CRC-16 OF COMMAND, ADDRESS, DATA Y Y Y MASTER Tx RESET? N MASTER Rx "1"s MASTER Rx "1"s N MASTER Tx RESET? Y FROM FIGURE 10b TO ROM FUNCTIONS FLOWCHART (FIGURE 13) Figure 10a. Memory/Control Function Flowchart 22 ______________________________________________________________________________________ Thermochron iButton DS1921G FROM FIGURE 10a F0h READ MEMORY? Y DS1921G SETS EMCLR = 0 N A5h READ MEMORY WITH CRC Y DS1921G SETS EMCLR = 0 DECISION MADE BY DS1921G N 3Ch CLEAR MEMORY Y N TO FIGURE 10c EMCLR = 1? Y DS1921G CLEARS MISSION TIMESTAMP, MISSION SAMPLES COUNTER, MISSION START DELAY, SAMPLE RATE REGISTER N MASTER Rx TA1 [T7:T0], TA2 [T15:T8] MASTER Tx TA1 [T7:T0], TA2 [T15:T8] DS1921G SETS MEMORY ADDRESS = [T15:T0] DECISION MADE BY MASTER DS1921G INCREMENTS ADDRESS COUNTER Y MASTER Rx DATA BYTE FROM MEMORY ADDRESS Y DS1921G SETS MEMORY ADDRESS = [T15:T0] END OF MEMORY? N DS1921G CLEARS ALARM TIMESTAMPS AND DURATIONS MASTER Tx RESET? N MASTER Rx 00 BYTE MASTER Rx DATA BYTE FROM MEMORY ADDRESS DS1921G CLEARS HISTOGRAM MEMORY N END OF MEMORY? Y MASTER Rx "0" Y MASTER Tx RESET? N DS1921G INCREMENTS ADDRESS COUNTER DS1921G SETS MEMCLR = 1 DS1921G SETS EMCLR = 0 END OF PAGE? Y N N MASTER Tx RESET? Y MASTER Rx CRC-16 OF COMMAND, ADDRESS, DATA (1ST PASS); CRC-16 OF DATA (SUBSEQUENT PASSES) CRC OK? N MASTER Tx RESET Y TO FIGURE 10a FROM FIGURE 10c Figure 10b. Memory/Control Function Flowchart ______________________________________________________________________________________ 23 Thermochron iButton DS1921G FROM FIGURE 10b 44h CONVERT TEMPERATURE? Y DS1921G SETS EMCLR = 0 N TEMPERATURE CONVERSION PROCESS Y MISSION IN PROGRESS? N DS1921G STARTS TEMPERATURE CONVERSION PROCESS DS1921G SETS TCB = 0 DS1921G PERFORMS A TEMPERATURE CONVERSION DS1921G COPIES RESULT TO ADDRESS 0211h N MASTER Tx RESET? Y DS1921G SETS TCB = 1 END OF PROCESS N MASTER Tx RESET? Y TO FIGURE 10b Figure 10c. Memory/Control Function Flowchart 24 ______________________________________________________________________________________ Thermochron iButton Read Memory with CRC [A5h] The Read Memory with CRC command is used to read memory data that cannot be packetized, such as the register page and the data recorded by the device during a mission. The command works the same way as the simple Read Memory command, except for the 16bit CRC that the DS1921G generates and transmits following the last data byte of a memory page. After having sent the command code of the Read Memory with CRC command, the bus master sends a 2-byte address (TA1 = T[7:0], TA2 = T[15:8]) that indicates a starting byte location. With the subsequent read-data time slots, the master receives data from the DS1921G starting at the initial address and continues until the end of a 32-byte page is reached. At that point the bus master sends 16 additional read-data time slots and receives an inverted 16-bit CRC. With subsequent read-data time slots the master receives data starting at the beginning of the next page followed again by the inverted CRC for that page. This sequence continues until the bus master resets the device. With the initial pass through the Read Memory with CRC command flow, the 16-bit CRC value is the result of shifting the command byte into the cleared CRC generator followed by the two address bytes and the contents of the data memory. Subsequent passes through the Read Memory with CRC command flow generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in the contents of the data memory page. After the 16-bit CRC of the last page is read, the bus master receives logical "0"s from the DS1921G and inverted CRC-16s at page boundaries until a reset pulse is issued. The Read Memory with CRC command sequence can be ended at any point by issuing a reset pulse. When the command is completed the MEMCLR bit in the Status register reads 1 and the EMCLR bit is 0. DS1921G Convert Temperature [44h] If a mission is not in progress (MIP = 0), the Convert Temperature command can be issued to measure the current temperature of the device. The result of the temperature conversion can be found at memory address 211h in the register page. This command takes maximum 90ms to complete. During this time the device remains fully accessible for memory/control and ROM function commands. Mission Start and Logging Process The DS1921G does not use a special command to start a mission. Instead, a mission is started by writing a nonzero value to the Sample Rate register using the Copy Scratchpad command. As shown in Figure 11, a new mission can only be started if the previous mission has been stopped (MIP = 0), the memory is cleared (MEMCLR = 1), and the mission is enabled (EM = 0). If the new sample rate is different from zero, the value is copied to the Sample Rate register. At the same time the MIP bit is set and the MEMCLR bit is cleared to indicate that the device is on a mission. Next, the Mission Start Delay Counter starts decrementing every minute until it is down to 0. Now the DS1921G waits until the next minute boundary and starts the logging process, which as its first action copies the applicable RTC registers to the Mission Timestamp register. Stop Mission The DS1921G does not have a special command to stop a mission. A mission can be stopped at any time by writing to any address in the range of 0200h to 0213h or by writing the MIP bit of the Status register at address 0214h to 0. Either approach involves the use of the Copy Scratchpad command. There is no need for the Mission Start Delay to expire before a mission can be stopped (see Figure 11). Clear Memory [3Ch] The Clear Memory command is used to clear the Sample Rate, Mission Start Delay, Mission Timestamp, and Mission Samples Counter in the register page and the temperature alarm memory and the temperature histogram memory. These memory areas must be cleared for the device to be set up for another mission. The Clear Memory command does not clear the datalog memory or the temperature and timer alarm flags in the Status register. The RTC oscillator must be on and have counted at least 1s before issuing the command. For the Clear Memory command to function, the EMCLR bit in the Control register must be set to 1, and the Clear Memory command must be issued with the very next access to the device's memory functions. Issuing any other memory function command resets the EMCLR bit. The Clear Memory process takes 500s. Memory Access Conflicts While a mission is in progress, a temperature sample is periodically taken and stored in the data-log, histogram, and potential alarm memory. This "internal activity" has priority over a Read Memory command's or Read Memory with CRC command's access to these pages. If a conflict occurs, the data read may be invalid, even if the CRC value matches the data. To ensure that the data read is valid, it is recommended to first read the SIP bit of the Status register. If the SIP bit is set, delay reading the data-log, histogram, and alarm memory until SIP is 0. The interference is more likely to be seen with a high sample rate (one sample every 25 ______________________________________________________________________________________ Thermochron iButton DS1921G MISSION START PROCESS LOGGING PROCESS MIP = 1? N Y DS1921G COPIES RTC TO MISSION TIMESTAMP DS1921G SETS MIP = 0 N DS1921G SETS DATA-LOG ADDRESS = 1000h EM = 0? Y DS1921G MEASURES TEMPERATURE N DS1921G UPDATES HISTOGRAM, DEVICE SAMPLES COUNTER, MISSION SAMPLES COUNTER AND ALARM, IF APPLICABLE Y N Y MEMCLR = 1? Y NEW SAMPLE RATE = 0? N DS1921G COPIES NEW SAMPLE RATE FROM SCRATCHPAD TO SAMPLE RATE REGISTER RO = 1? Y DATA-LOG ADDRESS = 1800h? N DS1921G SETS MIP = 1; MEMCLR = 0 DS1921G STORES TEMPERATURE AT DATA-LOG ADDRESS DS1921G STORES TEMPERATURE AT DATA-LOG ADDRESS START DELAY COUNTER = 0? N Y DS1921G INCREMENTS DATA-LOG ADDRESS DS1921G INCREMENTS LOWER 11 BITS OF DATA-LOG ADDRESS MIP = 1? Y DS1921G WAITS UNTIL NEXT MINUTE BOUNDARY N DS1921G WAITS UNTIL NEXT MINUTE BOUNDARY DS1921G WAITS ONE SAMPLE PERIOD DS1921G LOGGING PROCESS Y MIP = 1? N END OF PROCESS DS1921G DECREMENTS START DELAY COUNTER END OF PROCESS NOTE: THE MISSION START PROCESS IS INVOKED WHEN THE COPY SCRATCHPAD COMMAND IS USED TO SET A NEW SAMPLE RATE BY WRITING TO THE SAMPLE RATE REGISTER AT ADDRESS 020Dh. ONE MINUTE AFTER THE START DELAY COUNTDOWN IS OVER, THE LOGGING PROCESS BEGINS AND THE MISSION START PROCESS ENDS. Figure 11. Mission Start and Logging Process 26 ______________________________________________________________________________________ Thermochron iButton minute). Since all mission samples occur on the seconds rollover (59 to 00), memory conflicts can be avoided by first reading the RTC seconds counter. For example, if it takes 2s to read the data log, then avoid starting the memory read if the seconds counter is 58, 59, or 00. Alternatively, one can read the affected memory section twice and accept the data only if both readings match. In any case, when writing driver software, it is important to know about the possibility of interference and to take measures to work around it. a maximum data rate of 16.3kbps. The speed can be boosted to 142kbps by activating the overdrive mode. The DS1921G is not guaranteed to be fully compliant to the iButton standard. Its maximum data rate in standard speed is 15.4kbps and 125kbps in overdrive. The value of the pullup resistor primarily depends on the network size and load conditions. The DS1921G requires a pullup resistor of maximum 2.2k at any speed. The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 16s (overdrive speed) or more than 120s (standard speed), one or more devices on the bus may be reset. Note that the DS1921G does not quite meet the full 16s maximum low time of the normal 1-Wire bus overdrive timing. With the DS1921G the bus must be left low for no longer than 15s at overdrive speed to ensure that no DS1921G on the 1-Wire bus performs a reset. The DS1921G communicates properly when used in conjunction with a DS2480B or DS2490 1-Wire driver and adapters that are based on these driver chips. DS1921G 1-Wire Bus System The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the DS1921G is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). The 1-Wire protocol defines bus transactions in terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from the bus master. Hardware Configuration The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open-drain or three-state outputs. The 1-Wire port of the DS1921G is open drain with an internal circuit equivalent to that shown in Figure 12. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At standard speed the 1-Wire bus has Transaction Sequence The protocol for accessing the DS1921G through the 1-Wire port is as follows: * Initialization * ROM Function Command * Memory/Control Function Command * Transaction/Data VPUP BUS MASTER RPUP Rx DATA Rx DS1921G 1-Wire PORT Tx IL Rx = RECEIVE Tx = TRANSMIT OPEN-DRAIN PORT PIN 100 MOSFET Tx Figure 12. Hardware Configuration ______________________________________________________________________________________ 27 Thermochron iButton DS1921G Initialization All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master, followed by presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS1921G is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. value of the bit to be selected. All slave devices that do not match the bit written by the master stop participating in the search. If both of the read bits are zero, the master knows that slave devices exist with both states of the bit. By choosing which state to write, the bus master branches in the ROM code tree. After one complete pass, the bus master knows the registration number of a single device. Additional passes identify the registration numbers of the remaining devices. Refer to Application Note 187: 1-Wire Search Algorithm for a detailed discussion, including an example. ROM Function Commands Once the bus master has detected a presence, it can issue one of the seven ROM function commands. All ROM function commands are 8 bits long. A list of these commands follows (see the flowchart in Figure 13). Conditional Search ROM [ECh] The Conditional Search ROM command operates similarly to the Search ROM command except that only devices fulfilling the specified condition participate in the search. The condition is specified by the bit functions TAS, THS, and TLS in the Control register, address 20Eh. The Conditional Search ROM provides an efficient means for the bus master to determine devices on a multidrop system that have to signal an important event, such as a temperature leaving the tolerance band. After each pass of the conditional search that successfully determined the 64-bit ROM code for a specific device on the multidrop bus, that particular device can be individually accessed as if a Match ROM command had been issued, since all other devices have dropped out of the search process and are waiting for a reset pulse. For the conditional search, one can select any combination of the three search conditions by writing the associated bit to a logical 1. These bits correspond directly to the flags in the Status register of the device. If the flag in the Status register reads 1 and the corresponding bit in the Control register is a logical 1 too, the device responds to the Conditional Search ROM command. If more than one bit search condition is selected, the first event that occurs makes the device respond to the Conditional Search ROM command. Read ROM [33h] This command allows the bus master to read the DS1921G's 8-bit family code, unique 48-bit serial number and 8-bit CRC. This command can only be used if there is a single slave on the bus. If more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). The resultant family code and 48-bit serial number result in a mismatch of the CRC. Match ROM [55h] The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS1921G on a multidrop bus. Only the DS1921G that exactly matches the 64-bit ROM sequence responds to the memory function command. All other slaves wait for a reset pulse. This command can be used with a single device or multiple devices on the bus. Search ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their registration numbers. By taking advantage of the wired-AND property of the bus, the master can use a process of elimination to identify the registration numbers of all slave devices. For each bit of the registration number, starting with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each slave device participating in the search outputs the true value of its registration number bit. On the second slot, each slave device participating in the search outputs the complemented value of its registration number bit. On the third slot, the master writes the true Skip ROM [CCh] This command can save time in a single-drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for example, a read command is issued following the Skip ROM command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result). 28 ______________________________________________________________________________________ Thermochron iButton DS1921G FROM MEMORY/CONTROL FUNCTIONS FLOWCHART (FIGURE 10) MASTER Tx RESET PULSE FROM FIGURE 13b SHORT RESET PULSE? N OD = 0 Y MASTER Tx ROM FUNCTION COMMAND * DS1921G Tx PRESENCE PULSE ** 33h READ ROM COMMAND? Y N 55h MATCH ROM COMMAND? Y N F0h SEARCH ROM COMMAND? Y N ECh CONDITIONAL SEARCH COMMAND? Y N TO FIGURE 13b N CONDITION MET? Y DS1921G Tx FAMILY CODE (1 BYTE) DS1921G Tx BIT 0 * MASTER Tx BIT 0 * DS1921G Tx BIT 0 MASTER Tx BIT 0 * * * DS1921G Tx BIT 0 DS1921G Tx BIT 0 MASTER Tx BIT 0 * * * BIT 0 MATCH? N N BIT 0 MATCH? N BIT 0 MATCH? Y DS1921G Tx SERIAL NUMBER (6 BYTES) Y DS1921G Tx BIT 1 Y * MASTER Tx BIT 1 DS1921G Tx BIT 1 MASTER Tx BIT 1 * * * DS1921G Tx BIT 1 DS1921G Tx BIT 1 MASTER Tx BIT 1 * * * BIT 1 MATCH? N N BIT 1 MATCH? Y DS1921G Tx BIT 63 N BIT 1 MATCH? Y DS1921G Tx BIT 63 DS1921G Tx BIT 63 MASTER Tx BIT 63 Y DS1921G Tx CRC BYTE * MASTER Tx BIT 63 DS1921G Tx BIT 63 MASTER Tx BIT 63 * * * * * * BIT 63 MATCH? N N BIT 63 MATCH? N BIT 63 MATCH? Y Y Y TO FIGURE 13b FROM FIGURE 13b *TO BE TRANSMITTED OR RECEIVED AT OVERDRIVE SPEED IF OD = 1. ** PRESENCE PULSE IS SHORT IF OD = 1. TO MEMORY FUNCTIONS FLOWCHART (FIGURE 10) Figure 13a. ROM Functions Flowchart ______________________________________________________________________________________ 29 Thermochron iButton DS1921G TO FIGURE 13a FROM FIGURE 13a CCh SKIP ROM COMMAND? Y N 3Ch OVERDRIVESKIP ROM? Y OD = 1 N 69h OVERDRIVEMATCH ROM? Y OD = 1 N MASTER Tx RESET PULSE? N Y MASTER Tx BIT 0 *** BIT 0 MATCH? N Y MASTER Tx BIT 1 *** BIT 1 MATCH? N Y MASTER Tx BIT 63 *** BIT 63 MATCH? N FROM FIGURE 13a Y TO FIGURE 13a ***ALWAYS TO BE TRANSMITTED AT OVERDRIVE SPEED. Figure 13b. ROM Functions Flowchart 30 ______________________________________________________________________________________ Thermochron iButton Overdrive-Skip ROM [3Ch] On a single-drop bus this command can save time by allowing the bus master to access the memory/control functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command, the Overdrive-Skip ROM command sets the DS1921G in the overdrive mode (OD = 1). All communication following this command must occur at overdrive speed until a reset pulse of minimum 480s duration resets all devices on the bus to standard speed (OD = 0). When issued on a multidrop bus, this command sets all overdrive-supporting devices into overdrive mode. To subsequently address a specific overdrive-supporting device, a reset pulse at overdrive speed must be issued followed by a Match ROM or Search ROM command sequence. This speeds up the time for the search process. If more than one slave supporting overdrive is present on the bus and the Overdrive-Skip ROM command is followed by a read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wiredAND result). standard speed at the next reset pulse of minimum 480s duration. The Overdrive-Match ROM command can be used with a single or multiple devices on the bus. DS1921G 1-Wire Signaling The DS1921G requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on one line: reset sequence with reset pulse and presence pulse, write-zero, write-one, and read-data. Except for the presence pulse, the bus master initiates all these signals. The DS1921G can communicate at two different speeds: standard speed and overdrive speed. If not explicitly set into the overdrive mode, the DS1921G communicates at standard speed. While in overdrive mode, the fast timing applies to all waveforms. To get from idle to active, the voltage on the 1-Wire line needs to fall from VPUP below the threshold VTL. To get from active to idle, the voltage needs to rise from VILMAX past the threshold VTH. The time it takes for the voltage to make this rise is seen in Figure 14 as "" and its duration depends on the pullup resistor (RPUP) used and the capacitance of the 1-Wire network attached. The voltage VILMAX is relevant for the DS1921G when determining a logical level, but not for triggering any events. The initialization sequence required to begin any communication with the DS1921G is shown in Figure 14. A reset pulse followed by a presence pulse indicates the DS1921G is ready to receive data, given the correct ROM and memory function command. If the bus master uses slew-rate control on the falling edge, it must pull down the line for tRSTL + tF to compensate for the edge. Overdrive-Match ROM [69h] The Overdrive-Match ROM command followed by a 64bit ROM sequence transmitted at overdrive speed allows the bus master to address a specific DS1921G on a multidrop bus and to simultaneously set it in overdrive mode. Only the DS1921G that exactly matches the 64-bit ROM sequence responds to the subsequent memory/control function command. Slaves already in overdrive mode from a previous Overdrive-Skip or successful Overdrive-Match ROM command remain in overdrive mode. All overdrive-capable slaves return to MASTER Tx "RESET PULSE" VPUP VIHMASTER VTH VTL VILMAX 0V tRSTL tF tMSP MASTER Rx "PRESENCE PULSE" tPDH tPDL tRSTH tREC RESISTOR MASTER DS1921G Figure 14. Intitialization Procedure: Reset and Presence Pulses ______________________________________________________________________________________ 31 Thermochron iButton DS1921G A tRSTL duration of 480s or longer exits the overdrive mode, returning the device to standard speed. If the DS1921G is in overdrive mode and tRSTL is no longer than 80s, the device remains in overdrive mode. After the bus master has released the line, it goes into receive mode (Rx). Now the 1-Wire bus is pulled to V PUP through the pullup resistor or, in case of a DS2480B driver, through active circuitry. When the threshold VTH is crossed, the DS1921G waits for tPDH and then transmits a presence pulse by pulling the line low for tPDL. To detect a presence pulse, the master must test the logical state of the 1-Wire line at tMSP. The tRSTH window must be at least the sum of tPDHMAX, t PDLMAX , and t RECMIN . Immediately after t RSTH is expired, the DS1921G is ready for data communication. In a mixed population network, tRSTH should be extended to minimum 480s at standard speed and 48s at overdrive speed to accommodate other 1-Wire devices. The sum of tRL + (rise time) on one side and the internal timing generator of the DS1921G on the other side define the master sampling window (t MSRMIN to tMSRMAX) in which the master must perform a read from the data line. For most reliable communication, t RL should be as short as permissible and the master should read close to but no later than tMSRMAX. After reading from the data line, the master must wait until tSLOT is expired. This guarantees sufficient recovery time tREC for the DS1921G to get ready for the next time slot. CRC Generation There are two different types of CRCs with the DS1921G. One CRC is an 8-bit type and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS1921G to determine if the ROM data has been received error-free. The equivalent polynomial function of this CRC is X 8 + X 5 + X 4 + 1. This 8-bit CRC is received in the true (noninverted) form. It is computed at the factory and lasered into the ROM. The other CRC is a 16-bit type, generated according to the standardized CRC-16 polynomial function X16 + X15 + X2 + 1. This CRC is used for error detection when reading data memory using the Read Memory with CRC command and for fast verification of a data transfer when writing to or reading from the scratchpad. In contrast to the 8-bit CRC, the 16-bit CRC is always communicated in the inverted form. A CRC-generator inside the DS1921G chip (Figure 16) calculates a new 16-bit CRC as shown in the command flowchart of Figure 10. The bus master compares the CRC value read from the device to the one it calculates from the data and decides whether to continue with an operation or to reread the portion of the data with the CRC error. With the initial pass through the Read Memory with CRC flowchart, the 16-bit CRC value is the result of shifting the command byte into the cleared CRC generator, followed by the 2 address bytes and the data bytes. Subsequent passes through the Read Memory with CRC flowchart generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in the data bytes. With the Write Scratchpad command, the CRC is generated by first clearing the CRC generator and then shifting in the command code, the target addresses TA1 and TA2, and all the data bytes. The DS1921G transmits this CRC only if the data bytes written to the scratchpad include scratchpad ending offset 11111b. The data can start at any location within the scratchpad. Read/Write Time Slots Data communication with the DS1921G takes place in time slots that carry a single bit each. Write time slots transport data from bus master to slave. Read time slots transfer data from slave to master. The definitions of the write and read time slots are illustrated in Figure 15. All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line falls below the threshold VTL, the DS1921G starts its internal timing generator that determines when the data line is sampled during a write time slot and how long data is valid during a read time slot. Master-to-Slave For a write-one time slot, the voltage on the data line must have crossed the VTH threshold after the write-one low time tW1LMAX is expired. For a write-zero time slot, the voltage on the data line must stay below the VTH threshold until the write-zero low time tW0LMIN is expired. The voltage on the data line should not exceed VILMAX during the entire tW0L or tW1L window. After the VTH threshold has been crossed, the DS1921G needs a recovery time tREC before it is ready for the next time slot. Slave-to-Master A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below VTL until the read low time tRL is expired. During the tRL window, when responding with a 0, the DS1921G starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When responding with a 1, the DS1921G does not hold the data line low at all, and the voltage starts rising as soon as tRL is over. 32 ______________________________________________________________________________________ Thermochron iButton DS1921G WRITE-ONE TIME SLOT tW1L VPUP VIHMASTER VTH VTL VILMAX 0V tF tSLOT RESISTOR MASTER WRITE-ZERO TIME SLOT tW0L VPUP VIHMASTER VTH VTL VILMAX 0V tF tSLOT RESISTOR MASTER tREC READ-DATA TIME SLOT tMSR tRL VPUP VIHMASTER VTH VTL VILMAX 0V tF MASTER SAMPLING WINDOW tSLOT RESISTOR MASTER DS1921G tREC Figure 15. Read/Write Timing Diagram ______________________________________________________________________________________ 33 Thermochron iButton DS1921G With the Read Scratchpad command, the CRC is generated by first clearing the CRC generator and then shifting in the command code, the target addresses TA1 and TA2, the E/S byte, and the scratchpad data starting at the target address. The DS1921G transmits this CRC only if the reading continues through the end of the scratchpad, regardless of the actual ending offset. For more information on generating CRC values refer to Application Note 27: Understanding and Using Cyclic Redundancy Checks with Maxim iButton Products. POLYNOMIAL = X16 + X15 + X2 + 1 1ST STAGE X0 X1 2ND STAGE X2 3RD STAGE X3 4TH STAGE X4 5TH STAGE X5 6TH STAGE X6 7TH STAGE X7 8TH STAGE 9TH STAGE X8 X9 10TH STAGE X10 11TH STAGE X11 12TH STAGE X12 13TH STAGE X13 14TH STAGE X14 15TH STAGE X15 16TH STAGE X16 INPUT DATA CRC OUTPUT Figure 16. CRC-16 Hardware Description and Polynomial Command-Specific 1-Wire Communication Protocol--Legend SYMBOL RST PD Select WS RS CPS RM RMC CM CT TA TA-E/S 1-Wire reset pulse generated by master 1-Wire presence pulse generated by slave Command and data to satisfy the ROM function protocol (Skip ROM, Search ROM, etc.) Command: "Write Scratchpad" Command: "Read Scratchpad" Command: "Copy Scratchpad" Command: "Read Memory" Command: "Read Memory with CRC" Command: "Clear Memory" Command: "Convert Temperature" Target Address TA1, TA2 Target Address TA1, TA2 with E/S byte Transfer of as many data bytes as are needed to reach the scratchpad offset 1Fh Transfer of as many data bytes as are needed to reach the end of a memory page Transfer of as many data bytes as are needed to reach the end of the data-log memory DESCRIPTION 34 ______________________________________________________________________________________ Thermochron iButton Command-Specific 1-Wire Communication Protocol--Legend (continued) SYMBOL <00 to EOP> <32 bytes> CRC-16 FF loop AA loop 00 loop Transfer of 32 bytes Transfer of an undetermined amount of data Transfer of an inverted CRC-16 Indefinite loop where the master reads FFh bytes Indefinite loop where the master reads AAh bytes Indefinite loop where the master reads 00h bytes DESCRIPTION Transfer of as many 00h bytes as are needed to reach a memory page boundary DS1921G Command-Specific 1-Wire Communication Protocol--Color Codes Master-to-Slave Slave-to-Master 1-Wire Communication Examples Write Scratchpad, Reaching the End of the Scratchpad RST PD Select WS TA CRC-16 FF loop Write Scratchpad, Not Reaching the End of the Scratchpad RST PD Select WS TA RST PD Read Scratchpad RST PD Select RS TA-E/S CRC-16 FF loop Copy Scratchpad (Success) RST PD Select CPS TA-E/S AA loop Copy Scratchpad (Invalid TA-E/S) RST PD Select CPS TA-E/S FF loop Read Memory (Success) RST PD Select RM TA 00 loop Read Memory (Invalid Address) RST PD Select RM TA 00 loop Reading reserved pages 20 through 63 or 68 through 127 or pages 192 and higher (beyond data-log memory) results in 00h bytes. ______________________________________________________________________________________ 35 Thermochron iButton DS1921G 1-Wire Communication Examples (continued) Read Memory with CRC (Success) RST PD Select RMC TA CRC-16 <32 bytes> Loop CRC-16 The "32 bytes" are either valid page data or 00h bytes when reading reserved pages 20 through 63 or 68 through 127 or pages 192 and higher (beyond data-log memory). Read Memory with CRC (Invalid Address) RST PD Select RMC TA <00 to EOP> CRC-16 <32 bytes> Loop CRC-16 The "32 bytes" are all 00h. Clear Memory RST PD Select CM FF loop To verify success, read the Status register at address 0214h. If MEMCLR is 1, the command was executed successfully. Convert Temperature RST PD Select CT FF loop To read the result and to verify success, read the addresses 0211h (result) and the Device Samples Counter at address 021Dh to 021Fh. If the count has incremented, the command was executed successfully. Mission Example: Prepare and Start a New Mission Assumption: The previous mission has ended. To end an ongoing mission write the MIP bit in the Status register to 0. The preparation of a DS1921G for a mission including the start of the mission requires up to four steps: Step 1: Set the RTC (if it needs to be adjusted). Step 2: Clear the data of the previous mission. Step 3: Set the search condition and Mission Start Delay and clear the alarm flags. Step 4: Set the temperature alarms and write the Sample Rate to start the mission. 36 ______________________________________________________________________________________ Thermochron iButton Step 1: Set the RTC Let the actual time be 15:30:00 hours on Monday, the 1st of April in 2002. This results in the following data to be written to the RTC registers: ADDRESS DATA 200h 00h 201h 30h 202h 15h 203h 01h 204h 81h 205h 04h 206h 02h DS1921G With only a single DS1921G connected to the bus master, the communication of step 1 is as follows: MASTER MODE Tx Rx Tx Tx Tx Tx Tx Tx Rx Tx Tx Rx Rx Rx Rx Tx Rx Tx Tx Tx Tx Tx Tx Rx DATA (LSB FIRST) (Reset) (Presence) CCh 0Fh 00h 02h <7 data bytes> (Reset) (Presence) CCh AAh 00h 02h 06h <7 data bytes> (Reset) (Presence) CCh 55h 00h 02h 06h (Reset) (Presence) Presence pulse Issue Skip ROM command Issue Write Scratchpad command TA1, beginning offset = 00h TA2, address = 0200h Write 7 bytes of data to scratchpad Reset pulse Presence pulse Issue Skip ROM command Issue Read Scratchpad command Read TA1, beginning offset = 00h Read TA2, address = 0200h Read E/S, ending offset = 6h, flags = 0h Read scratchpad data and verify Reset pulse Presence pulse Issue Skip ROM command Issue Copy Scratchpad command TA1 TA2 E/S Reset pulse Presence pulse (AUTHORIZATION CODE) COMMENTS Reset pulse (480s to 960s) ______________________________________________________________________________________ 37 Thermochron iButton DS1921G Step 2: Clear the data of the previous mission Set the EMCLR bit to 1, enable the RTC, and then execute the Clear Memory command. The RTC oscillator must be stable before the Clear Memory command is issued. Wait 500s after issuing the Clear Memory command before proceeding to step 3. This results in the following data to be written to the Status register: ADDRESS DATA 20Eh 40h With only a single DS1921G connected to the bus master, the communication of step 2 is as follows: MASTER MODE Tx Rx Tx Tx Tx Tx Tx Tx Rx Tx Tx Rx Rx Rx Rx Tx Rx Tx Tx Tx Tx Tx Tx Rx Tx Tx Tx Rx DATA (LSB FIRST) (Reset) (Presence) CCh 0Fh 0Eh 02h 40h (Reset) (Presence) CCh AAh 0Eh 02h 0Eh 40h (Reset) (Presence) CCh 55h 0Eh 02h 0Eh (Reset) (Presence) CCh 3Ch (Reset) (Presence) Presence pulse Issue Skip ROM command Issue Write Scratchpad command TA1, beginning offset = 0Eh TA2, address = 020Eh Write status byte to scratchpad Reset pulse Presence pulse Issue Skip ROM command Issue Read Scratchpad command Read TA1, beginning offset = 0Eh Read TA2, address = 020Eh Read E/S, ending offset = 0Eh, flags = 0h Read scratchpad data and verify Reset pulse Presence pulse Issue Skip ROM command Issue Copy Scratchpad command TA1 TA2 E/S Reset pulse Presence pulse Issue Skip ROM command Issue Clear Memory command Reset pulse Presence pulse (AUTHORIZATION CODE) COMMENTS Reset pulse (480s to 960s) 38 ______________________________________________________________________________________ Thermochron iButton Step 3: Set the search condition and Mission Start Delay and clear the alarm flags In this example, the rollover is disabled and the search condition is set for a high temperature only. The mission is to start with a delay of 90min (005Ah) and the alarm flags TLF, THF, and TAF are cleared. This results in the following data to be written to the special function registers: ADDRESS DATA 20Eh 02h 20Fh 00h* 210h 00h* 211h 00h* 212h 5Ah 213h 00h 214h 00h DS1921G *Writing through address locations 20Fh to 211h is faster than accessing the Mission Start Delay register in a separate cycle. The write attempt has no effect on the contents of these registers. With only a single DS1921G connected to the bus master, the communication of step 3 is as follows: MASTER MODE Tx Rx Tx Tx Tx Tx Tx Tx Rx Tx Tx Rx Rx Rx Rx Tx Rx Tx Tx Tx Tx Tx Tx Rx DATA (LSB FIRST) (Reset) (Presence) CCh 0Fh 0Eh 02h <7 data bytes> (Reset) (Presence) CCh AAh 0Eh 02h 14h <7 data bytes> (Reset) (Presence) CCh 55h 0Eh 02h 13h (Reset) (Presence) Presence pulse Issue Skip ROM command Issue Write Scratchpad command TA1, beginning offset = 0Eh TA2, address = 020Eh Write 7 bytes of data to scratchpad Reset pulse Presence pulse Issue Skip ROM command Issue Read Scratchpad command Read TA1, beginning offset = 0Eh Read TA2, address = 020Eh Read E/S, ending offset = 14h, flags = 0h Read scratchpad data and verify Reset pulse Presence pulse Issue Skip ROM command Issue Copy Scratchpad command TA1 TA2 E/S Reset pulse Presence pulse (AUTHORIZATION CODE) COMMENTS Reset Pulse (480s to 960s) ______________________________________________________________________________________ 39 Thermochron iButton DS1921G Step 4: Set the temperature alarms and write the Sample Rate to start the mission In this example, the temperature alarms are set to -5C for the low temperature threshold and 0C for the high temperature threshold. The sample rate is once every 10min, allowing the mission to last up to 14 days. This results in the following data to be written to the special function registers: ADDRESS DATA 20Bh 46h 20Ch 50h 20Dh 0Ah With only a single DS1921G connected to the bus master, the communication of step 4 is as follows: MASTER MODE Tx Rx Tx Tx Tx Tx Tx Tx Rx Tx Tx Rx Rx Rx Rx Tx Rx Tx Tx Tx Tx Tx Tx Rx DATA (LSB FIRST) (Reset) (Presence) CCh 0Fh 0Bh 02h <3 data bytes> (Reset) (Presence) CCh AAh 0Bh 02h 0Dh <3 data bytes> (Reset) (Presence) CCh 55h 0Bh 02h 0Dh (Reset) (Presence) Presence pulse Issue Skip ROM command Issue Write Scratchpad command TA1, beginning offset = 0Bh TA2, address = 020Bh Write 3 bytes of data to scratchpad Reset pulse Presence pulse Issue Skip ROM command Issue Read Scratchpad command Read TA1, beginning offset = 0Bh Read TA2, address = 020Bh Read E/S, ending offset = 0Dh, flags = 0h Read scratchpad data and verify Reset pulse Presence pulse Issue Skip ROM command Issue Copy Scratchpad command TA1 TA2 E/S Reset pulse Presence pulse (AUTHORIZATION CODE) COMMENTS Reset pulse (480s to 960s) If step 4 is successful, the MIP bit in the Status register is 1, the MEMCLR bit is 0, and the Mission Start Delay counts down. 40 ______________________________________________________________________________________ Thermochron iButton Pin Configuration 5.89mm 0.51mm BRANDING Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. DS1921G iB ut t o n (R). c om (R) 21 16.25mm 000000FBC52B W Thermochrom G W Z Z Z DS 1 9 2 1 -F 1-Wire(R) (R) 89 PACKAGE TYPE F5 iButton PACKAGE CODE IB#5CP OUTLINE NO. 21-0266 LAND PATTERN NO. -- 5 YY 17.35mm IO GND ______________________________________________________________________________________ 41 Thermochron iButton DS1921G Revision History REVISION DATE DESCRIPTION Added bullet "Water resistant or waterproof if placed inside DS9107 iButton capsule (Exceeds Water Resistant 3 ATM requirements)" Deleted "application pending" from UL bullet and safety statement 120407 Added text to Detailed Description section: Note that the initial sealing level of DS1921G achieves IP56. Aging and use conditions can degrade the integrity of the seal over time, so for applications with significant exposure to liquids, sprays, or other similar environments, it is recommended to place the Thermochron in the DS9107 iButton capsule. The DS9107 provides a watertight enclosure that has been rated to IP68 (See www.maxim-ic.com/AN4126) Created newer template-style data sheet Overdrive specifications for tRSTL, tPDL, and tW0L split into range VPUP > 4.5V and full range. New values for the full range Updated UL certificate reference; deleted from the tW1L specification in the Electrical Characteristics table; applied note 13 to the tW0L specification in the Electrical Characteristics table; added more details to Electrical Characteristics table notes 7, 13, and 14 1, 2 PAGES CHANGED 4/09 4/10 All 2-4 4/11 1, 3, 4 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 42 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. |
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